Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation

Strain techniques have been adopted and widely used in the advanced nodes since early 65 nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process could lead strain relaxation caused by implant damage. In this paper, cryo-implantation technology is applied and characterization of strain relaxation is conducted using a state-of-the-art 28 nm CMOS process flow. Experimental results indicate strain relaxation can be reduced with cryo implants relative to the room temperature implants. This study clearly showed that cryo-implantion reduced damage formation resulting in junction leakage reduction.