Title :
Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation
Author :
Li, C.I. ; Yang, C.L. ; Hsieh, H.Y. ; Lin, G.P. ; Liu, R. ; Wang, H.Y. ; Hsu, B.C. ; Chan, M. ; Wu, J.Y. ; Chen, I.C. ; Guo, B.N. ; Colombeau, B. ; Shim, K.H. ; Wu, T. ; Sun, H.L. ; Lu, S.
Author_Institution :
Central R&D Div., United Microelectron. Corp., Tainan, Taiwan
Abstract :
Strain techniques have been adopted and widely used in the advanced nodes since early 65 nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process could lead strain relaxation caused by implant damage. In this paper, cryo-implantation technology is applied and characterization of strain relaxation is conducted using a state-of-the-art 28 nm CMOS process flow. Experimental results indicate strain relaxation can be reduced with cryo implants relative to the room temperature implants. This study clearly showed that cryo-implantion reduced damage formation resulting in junction leakage reduction.
Keywords :
CMOS integrated circuits; Ge-Si alloys; carrier mobility; contact resistance; cryogenic electronics; ion implantation; semiconductor materials; CMOS process flow; PMOS device; PSD formation; SiGe; boron concentration; carrier mobility; compressive strain; contact resistance; cryoimplantation technology; junction leakage reduction; size 28 nm; size 65 nm; strain techniques; Annealing; Boron; Implants; Junctions; Silicon; Silicon germanium; Strain; Novel process technology; cryo implant; ion implantation; strain relaxation;
Conference_Titel :
Junction Technology (IWJT), 2011 11th International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
978-1-61284-131-1
DOI :
10.1109/IWJT.2011.5970002
