A scalable MRAM design capable of 10Gbits/chip and beyond

In this paper, we present a novel MRAM design that is capable of 50 Gbits/in² storage density and beyond with sufficient thermal stability and fabrication tolerance. The design utilizes perpendicular magnetic tunnel junction (Nishimura et al., 2002) as the memory element and the word lines and digital lines are arranged as shown in the figure below. The design yields 8F² memory cell area assuming the tunnel junction itself is 1F² in area where F denotes the fabrication minimum feature size. Micromagnetic simulations were performed for the element size of 40times40times40 nm³ to identify the single domain regime where magnetic switching becomes robust with little dependence on possible geometric variation introduced in practical fabrication processes. Noting in the single domain regime, the ratio of the perpendicular anisotropy energy constant and saturation magnetization of the storage layer, K/M_s , is the switching field, switching field around 100 Oe can be achieved with sufficient thermal magnetic stability (DeltaE > 80 k _BT) with a material of appropriate perpendicular anisotropy and saturation magnetization as indicated the results in the figure. The design with 40 nm square memory elements will yield close to 50 Gbits/in ² storage density