Characterization of total chip leakage using inverse (reciprocal) gamma distribution

Leakage is an important performance bottleneck in current digital integrated circuit technology. Many techniques were proposed to analyze, control and avoid leakage of a circuit, but all efforts need accurate characterizations of total leakage variations of a chip under real-life manufacturing and environmental parameter fluctuations. In this paper, we are proposing to apply a new statistical technique to model the overall distribution of total chip leakage under such variations. With our proposed model, chip designers and design automation tools can better assess and manage leakage power