Title :
Power-oriented delay budgeting for combinational circuits
Author :
Mi, Jialin ; Chen, Chunhong ; Kwan, H.K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Windsor Univ., Ont.
Abstract :
In this paper we propose an approach of providing the best power-delay tradeoff for combinational circuits. This is done by so-called power-oriented delay budgeting which is to combine the delay-budgeting technique with aggressive power optimization. We discuss the impacts that both discrete cell library and circuit topology may have on the potential power reduction. Experimental results show that up to 65% (an average of 35%) power savings can be achieved without any delay penalty
Keywords :
circuit optimisation; delay circuits; power integrated circuits; aggressive power optimization; combinational circuits; delay penalty; discrete cell library; potential power reduction; power-delay tradeoff; power-oriented delay budgeting; Circuit synthesis; Circuit topology; Combinational circuits; Design optimization; Digital systems; Energy consumption; Libraries; Logic functions; Propagation delay; Timing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693264
