DocumentCode
2543588
Title
Efficient don´t care computation for hierarchical designs
Author
Gulati, Kush ; Lovell, Matthew ; Khatri, Sunil P.
Author_Institution
Dept. of EE, Texas A & M Univ., College Station, TX
fYear
2006
fDate
21-24 May 2006
Lastpage
3040
Abstract
In this paper, we describe a BDD-based hierarchical don´t care computation algorithm. In contrast to traditional don´t care computation techniques, our method retains the hierarchy in the design netlist during the don´t care computation. Although this may reduce some of the flexibility inherent in the optimization process, it allows our technique to handle large designs. Our method computes don´t cares at input and output interfaces of different modules in the hierarchy by an image computation process. In case an exact image cannot be computed, our method computes the largest approximate image. Once the don´t cares at the input and output interfaces are computed, the hierarchical instances are optimized separately using a traditional optimization flow. Experimental results demonstrate that our technique can achieve a 36% reduction in literal count for large hierarchical designs, with reasonable runtimes. Our method can complete for several examples in which flattened optimization fails
Keywords
binary decision diagrams; circuit optimisation; logic design; multivalued logic; BDD; binary decision diagram; dont care computation; hierarchical designs; netlist; optimization process; Boolean functions; Buildings; Circuit synthesis; Computer interfaces; Data structures; Design optimization; Feeds; Logic; Optimization methods; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693265
Filename
1693265
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