Title :
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver
Author :
Wu, Yi-Da ; Chang-Ming Lai ; Chih-Yuan Chou ; Huang, Po-Chiun
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
Abstract :
A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth and settling time requirement. System analysis shows that this structure can meet the stringent requirement of DCS1800. This structure is designed with a 0.18 mum CMOS process. Excluding of DDS, the synthesizer core dissipates 9.5mW from a 1.8V supply
Keywords :
CMOS integrated circuits; direct digital synthesis; phase locked loops; radio receivers; 0.18 micron; 1.8 V; 9.5 mW; CMOS process; DCS-1800 receiver; OPLL-DDS based frequency synthesizer; channel selection; direct-digital synthesis; loop bandwidth; offset phase-locked loop; synthesizer core; Bandwidth; Channel spacing; Communication industry; Contacts; Frequency conversion; Frequency synthesizers; GSM; Mobile communication; Phase locked loops; Signal synthesis;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693271
