Title :
1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS
Author :
Han, Pyung-Su ; Choi, Woo-Young
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul
Abstract :
A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with 0.18-mum CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement
Keywords :
CMOS integrated circuits; clocks; high-speed integrated circuits; oscillators; synchronisation; 0.18 micron; 1.25 Gbit/s; 2.5 Gbit/s; CMOS integrated circuit; burst-mode clock recovery circuit; clock alignment; clocking mode; data edges; dual bit-rate structure; dual-mode operation; gated-oscillator; reset-phase control scheme; Area measurement; Clocks; Frequency; Jitter; Magnetic circuits; Passive optical networks; Prototypes; Ring oscillators; Surface acoustic waves; Throughput;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693273
