A channel-constrained reconfiguration approach for processing arrays

Author

Distante, F. ; Sami, M.G. ; Stefanelli, R.

Author_Institution

Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy

fYear

1995

fDate

13-15 Nov 1995

Firstpage

99

Lastpage

107

Abstract

Most previous reconfiguration approaches considered as main figure of merit, besides probability of survival, length of reconfigured paths and deduced complexity of the interconnection network from the resulting algorithm. In the present paper, interconnection complexity is taken as the guiding figure of merit and a reconfiguration algorithm based on a stringent channel width limitation is presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing presence of faults in bus segments and switches as well as in PEs

Keywords

fault tolerant computing; multiprocessor interconnection networks; parallel processing; reconfigurable architectures; bus segments; bus switches; channel-constrained reconfiguration approach; fault model; interconnection complexity; interconnection network; processing arrays; reconfiguration algorithm; stringent channel width limitation; Algorithm design and analysis; Capacity planning; Conferences; Design optimization; Fault tolerant systems; Logic arrays; Multiprocessor interconnection networks; Redundancy; Shape; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,

Conference_Location

Lafayette, LA

ISSN

1550-5774

Print_ISBN

0-8186-7107-6

Type

conf

DOI

10.1109/DFTVS.1995.476942

Filename

476942