Title :
A portable all-digital pulsewidth control loop for SOC applications
Author :
Wang, Wei ; Wey, I-Chyn ; Wu, Chia-Tsun ; Wu, An-Yeu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate system-level integration, the new design can be developed in hardware description language (HDL) and implemented with standard-cell libraries, therefore, easily portable between technologies. In addition, a high-resolution architecture is designed to enhance pulsewidth precision. For different requirements of applications, the characteristic of scalable modulating range allows hardware decision in early stage. The proposed methodology has been proven at UMC 0.18mum CMOS technology. When operated at 350 MHz, the pulse width acquisition ranges from 10% to 85% with 0.9% steps
Keywords :
CMOS integrated circuits; digital phase locked loops; integrated circuit design; system-on-chip; 0.18 micron; 350 MHz; CMOS technology; all-digital pulsewidth control loop; hardware description language; standard-cell libraries; system-level integration; system-on-chip; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Filters; Frequency conversion; Hardware design languages; Phase locked loops; Pulse circuits; Space vector pulse width modulation;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693297
