Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique

This paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to reduce operation delay. Designed and fabricated in 0.35mum 2P3M CMOS technology, FP3 works correctly as a multi-context FPGA. Our experimental results show that there exist cases where the best user circuit speed was achieved when 2 contexts were in use for a benchmark circuit. This is because of the reduction of buffers in the critical path by temporal partitioning.