Title :
Low power and high performance clock delayed domino logic using saturated keeper
Author :
Amirabadi, Amir ; Chehelcheraghi, A. ; Rasouli, S.H. ; Seyedi, Alireza ; Afzai-Kusha, A.
Author_Institution :
Dept. of ECE, Tehran Univ.
Abstract :
In this work, domino logic with a saturated keeper technique is proposed. The circuit, which is used to implement the technique, is as simple as the utilized NOT gate in standard domino. By using the simple structure, we can obtain better performance, noise immunity, and lower power consumption. The simulation results for a 70 nm CMOS technology show an improvement between 7% and 62.5% in delay and 9% and 14% in power consumption, over its previous suggestions
Keywords :
CMOS logic circuits; clocks; delays; logic gates; low-power electronics; nanotechnology; 70 nm; CMOS technology; NOT gate; clock delayed domino logic; noise immunity; power consumption; saturated keeper; CMOS technology; Circuit noise; Clocks; Delay; Energy consumption; Logic circuits; MOSFETs; Noise reduction; Phase noise; Routing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693299
