DocumentCode
2544302
Title
Energy Footprint of Advanced Dense Numerical Linear Algebra Using Tile Algorithms on Multicore Architectures
Author
Dongarra, Jack ; Ltaief, Hatem ; Luszczek, Piotr ; Weaver, Vincent M.
Author_Institution
Innovative Comput. Lab., Univ. of Tennessee, Knoxville, TN, USA
fYear
2012
fDate
1-3 Nov. 2012
Firstpage
274
Lastpage
281
Abstract
We propose to study the impact on the energy footprint of two advanced algorithmic strategies in the context of high performance dense linear algebra libraries: (1) mixed precision algorithms with iterative refinement allow to run at the peak performance of single precision floating-point arithmetic while achieving double precision accuracy and (2) tree reduction technique exposes more parallelism when factorizing tall and skinny matrices for solving over determined systems of linear equations or calculating the singular value decomposition. Integrated within the PLASMA library using tile algorithms, which will eventually supersede the block algorithms from LAPACK, both strategies further excel in performance in the presence of a dynamic task scheduler while targeting multicore architecture. Energy consumption measurements are reported along with parallel performance numbers on a dual-socket quad-core Intel Xeon as well as a quad-socket quad-core Intel Sandy Bridge chip, both providing component-based energy monitoring at all levels of the system, through the Power Pack framework and the Running Average Power Limit model, respectively.
Keywords
energy conservation; iterative methods; microprocessor chips; multiprocessing systems; power aware computing; scheduling; singular value decomposition; trees (mathematics); LAPACK; PLASMA library; block algorithm; component-based energy monitoring; dual-socket quad-core Intel Xeon; dynamic task scheduler; energy footprint; high performance dense linear algebra library; iterative refinement; matrix factorization; mixed precision algorithm; multicore architecture; power pack framework; quad-socket quad-core Intel Sandy Bridge chip; running average power limit model; single precision floating-point arithmetic; singular value decomposition; tile algorithm; tree reduction technique; Heuristic algorithms; Libraries; Linear algebra; Parallel processing; Plasmas; Power measurement; Tiles; Dense Linear Algebra; Dynamic Scheduling; Mixed Precision Algorithms; Power Consumption; PowerPack; RAPL; Tile Algorithms; Tree Reduction;
fLanguage
English
Publisher
ieee
Conference_Titel
Cloud and Green Computing (CGC), 2012 Second International Conference on
Conference_Location
Xiangtan
Print_ISBN
978-1-4673-3027-5
Type
conf
DOI
10.1109/CGC.2012.113
Filename
6382829
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