Title :
A Multi-Drop Transmission-Line Interconnect in Si LSI
Author :
Seita, Junki ; Ito, Hiroyuki ; Okada, Kenichi ; Sato, Takashi ; Masu, Kazuya
Author_Institution :
Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
Abstract :
This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; silicon; 0.18 micron; 4 Gbit/s; 6 mm; CMOS process; LSI; Si; branching method; multidrop rransmission-line interconnect; CMOS process; Capacitance; Degradation; Delay; Impedance; Integrated circuit interconnections; Large scale integration; Peer to peer computing; Power transmission lines; Transmission lines;
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
DOI :
10.1109/ASPDAC.2007.357969
