A 90nm 8Ã\x9716 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations

Author

Sugihara, Y. ; Kotani, M. ; Katsuki, K. ; Kobayashi, K. ; Onodera, H.

Author_Institution

Dept. of Commun. & Comput. Engeineering, Kyoto Univ.

fYear

2007

fDate

23-26 Jan. 2007

Firstpage

122

Lastpage

123

Abstract

We have fabricated an LUT-based FPGA device with functionalities measuring within-die variations in a 90nm process. Measured variations are used to configure each device to maximize the operating frequency by allocating critical paths in faster portions. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Placement optimization using a simple model circuit reveals that performance of the circuit is enhanced by 4% in average, which is the same amount as the measured within-die variations. The yield is enhanced by 32% to the worst case.

Keywords

field programmable gate arrays; nanotechnology; optimisation; table lookup; 90 nm; LUT-based FPGA device; placement optimization; ring oscillators; simple model circuit; within-die variations; Clocks; Counting circuits; Degradation; Field programmable gate arrays; Frequency conversion; Manufacturing; Ring oscillators; Semiconductor device measurement; Switches; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

1-4244-0629-3

Electronic_ISBN

1-4244-0630-7

Type

conf

DOI

10.1109/ASPDAC.2007.357971

Filename

4196017