• DocumentCode
    2544478
  • Title

    FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control

  • Author

    Viswanathan, Natarajan ; Pan, Min ; Chu, Chris

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
  • fYear
    2007
  • fDate
    23-26 Jan. 2007
  • Firstpage
    135
  • Lastpage
    140
  • Abstract
    In this paper, we present FastPlace 3.0 - an efficient and scalable multilevel quadratic placement algorithm for large-scale mixed-size designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a two-level clustering scheme within the flat analytical placer FastPlace (Viswanathan and Chu, 2005) and Viswanathan et al., 2006), (2) An efficient and improved iterative local refinement technique that can handle placement blockages and placement congestion constraints. (3) A congestion aware standard-cell legalization technique in the presence of blockages. On the ISPD-2005 placement benchmarks (Nam et al., 2005), our algorithm is 5.12times, 11.52times and 16.92times faster than mPL6, Capo10.2 and APlace2.0 respectively. In terms of wirelength, we are on average, 2% higher as compared to mPL6 and 9% and 3% better as compared to Capo10.2 and APlace2.0 respectively. We also achieve competitive results compared to a number of academic placers on the placement congestion constrained ISPD-2006 placement benchmarks (Nam, 2006).
  • Keywords
    circuit layout CAD; mixed analogue-digital integrated circuits; pattern clustering; quadratic programming; FastPlace 3.0; iterative local refinement; large-scale mixed-size designs; legalization technique; multilevel global placement framework; multilevel quadratic placement algorithm; placement blockages; placement congestion constraints; placement congestion control; two-level clustering scheme; Algorithm design and analysis; Analytical models; Circuit synthesis; Clustering algorithms; Iterative algorithms; Large-scale systems; Partitioning algorithms; Routing; Scalability; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    1-4244-0629-3
  • Electronic_ISBN
    1-4244-0630-7
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2007.357975
  • Filename
    4196021