The design and verification of a novel LDPC decoder with high-efficiency

A novel high-performance low density parity check codes (LDPC) decoder with small die size for IEEE802.16e criteria is presented in this paper. It utilizes the decoding technique called “Turbo Decoding Message Passing (TDMP)” and a new hardware architecture based on the Ping-Pong operation. Under the generic digital logic process of UMC, when the working frequency is 67MHz, the decoder presented in this paper has cell area of 7.19mm2, layout size of 10.72mm2, and maximum throughput of 1.1Gbps. The simulation results show that under AWGN channel with SNR of 3dB, the frame error rate of random code words is as low as 10-2.5. Compared with other papers, the LDPC decoder designed in this paper has a good error rate efficiency, higher throughput and smaller die size.