DocumentCode
2544683
Title
A Graph Reduction Approach to Symbolic Circuit Analysis
Author
Shi, Guoyong ; Chen, Weiwei ; Shi, C. J Richard
Author_Institution
Sch. of Microelectron., Shanghai Jiao Tong Univ.
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
197
Lastpage
202
Abstract
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.
Keywords
analogue circuits; circuit simulation; graph theory; symbol manipulation; binary decision diagram; graph reduction; recursive sign determination algorithm; symbolic analog circuit simulator; symbolic circuit analysis; Algorithm design and analysis; Analog circuits; Analytical models; Binary decision diagrams; Boolean functions; Circuit analysis; Circuit simulation; Data structures; Frequency domain analysis; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.357985
Filename
4196031
Link To Document