Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control

A digital phase locked loop (DPLL) has been developed in which the phase detection is performed by a bangbang phase detector (BBPD). By dithering the offset of the BBPD, its phase detection gain can be made to be constant and independent of the reference clock jitter. Therefore the bandwidth of the DPLL can be kept constant regardless of the magnitude of the reference clock jitter. The DPLL with the offset dithered BBPD has been implemented in a 65-nm CMOS process and occupies only 0.098-mm². The measurement results show the offset dithering of the BBPD has negligible effect on the period jitter of the DPLL output clock.