Title :
Vt-conscious repeater insertion in power-managed VLSI
Author :
Zarrabi, H. ; Al-Khalili, A. ; Savaria, Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada
Abstract :
In this paper, methods for the design space exploration of interconnection repeaters in deep-sub-micron power-managed VLSI are presented. These methods consider the system supply-voltage as well as the device threshold-voltage, as the design parameters; and guarantee that the designed interconnections are energy-optimal while they meet their performance objectives in all the system operating states. These methods take the output resistance of the repeaters into account, when the system supply-voltage, system operating frequency as well as the device threshold-voltage requirements change. Utilizing the proposed techniques, a multi-cycle 10-mm long bus is designed for some design objectives. HSPICE simulations confirm that the designed bus is energy-optimal, and that it meets its performance targets in all the system operating states.
Keywords :
VLSI; integrated circuit design; integrated circuit interconnections; HSPICE simulations; Vt-conscious repeater insertion; deep-sub-micron power-managed VLSI; design space exploration; device threshold-voltage; interconnection repeaters; multicycle long bus; system operating frequency; system operating states; system supply-voltage; Delays; Equations; Integrated circuit interconnections; Mathematical model; Performance evaluation; Repeaters; Very large scale integration; Dynamic Power Management; Interconnections; Repeater Insertion; VLSI;
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
DOI :
10.1109/ISICIR.2014.7029470
