A 20.5GHz wide-band programmable divide-by-N frequency divider

A 1.2V wide-band programmable divide-by-N frequency divider (FD) with consecutive 16-519 division ratios has been designed and fabricated using standard 90nm CMOS technology. The programmable FD consists of a high speed divide-by-8/9 dual-modulus prescaler, a pulse counter (P counter) and a swallow counter (S counter). Dynamic current-mode logic (DCML) DFF and signal locking technique have been used in this divider to achieve high speed operation. The proposed divider exhibits wide frequency range from 7GHz to 20.5GHz and dissipates 8.52mW power consumption at 1.2V voltage supply. Utilizing this FD, a charge-pump based PLL has been realized with 31.5GHz-34GHz frequency range. The phase noise of the PLL at 34.027GHz is -91.3dBc/Hz@1MHz offset. This PLL consumes 30.72mW power and occupies 1.32mm×1.01mm chip area.