Design of a 4 GS/s radix-1.75 single channel pipeline ADC in 28 nm CMOS technology with foreground calibration

This paper describes the architecture and schematic design of a 4 GS/s radix-1.75 pipeline ADC in 28 nm CMOS technology. Due to large mismatch effects, a foreground calibration procedure with characterization of the transfer functions of the single pipeline stages is necessary. The gained information is used in a pure digital backend calculation. This allows increasing the effective resolution to values above 6 bit up to the Nyquist-frequency. The converters maximum power consumption is 65 mW and the FOM is below 254 fJ per conversion step.