DocumentCode :
2544906
Title :
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks
Author :
Tan Yan ; Li, Shuting ; Takashima, Yasuhiro ; Murata, Hiroshi
Author_Institution :
Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka
fYear :
2007
fDate :
23-26 Jan. 2007
Firstpage :
268
Lastpage :
273
Abstract :
How to estimate the shortest routing length when certain blocks are considered as routing obstacles is becoming an essential problem for block placement because HPWL, is no longer valid in this case. Although this problem is well studied in computational geometry (Mitchell, 2000), the research results are neither well-known to the CAD community nor presented in a way easy for CAD researchers to ultilize their establishment. With the help of some recent notions in block placement, this paper interprets the research result in Atallah and Chen (1991) and de Rezende et al. (1985), which gives the best algorithm for this problem as we know, in a way more concise and more friendly to CAD researchers. Besides, we also tailor its algorithm to VLSI CAD application. As the result, we present a method that estimates the shortest obstacle-avoiding routing length in 0(M2 + N) time for a placement with M blocks and N 2-pin nets.
Keywords :
circuit layout CAD; computational complexity; integrated circuit interconnections; VLSI CAD; block placement; computational geometry; routing obstacles; shortest obstacle-avoiding routing length; shortest routing length; wire length estimation algorithms; Computational geometry; Design automation; Pins; Radio frequency; Routing; Statistical distributions; Timing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
Type :
conf
DOI :
10.1109/ASPDAC.2007.357997
Filename :
4196043
Link To Document :
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