Title :
A digital calibration technique for multi-bit-per-stage pipelined ADC
Author :
Yajuan He ; Song Wang ; Qi Ling ; Qiang Li
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
In this paper, a digital calibration algorithm, based on original radix 2 off-line algorithm, is employed to calibrate a 4 stages, 12 bits pipelined Analog-to-Digital Converter(ADC). The detail implementation process of this algorithm, from algorithm design to circuit structure, is presented. The simulation results show that the calibrated ADC achieves SNR of 73.9 dB, SNDR of 73.3 dB, SFDR of 84.2 dB, DNL of 0.47 LSB and INL of 0.84 LSB.
Keywords :
analogue-digital conversion; calibration; network synthesis; SNR; analog-to-digital converter; digital calibration technique; multibit-per-stage pipelined ADC; noise figure 73.3 dB; noise figure 73.9 dB; noise figure 84.2 dB; radix 2 off-line algorithm; word length 12 bit; Algorithm design and analysis; Analog-digital conversion; Calibration; Capacitors; Digital circuits; Operational amplifiers; Voltage measurement;
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
DOI :
10.1109/ISICIR.2014.7029485
