Title :
A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy
Author :
Kun Ao ; Yajuan He ; Liang Li ; Yuxin Wang ; Qiang Li
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A 14-b 100-MS/s pipeline analog-to-digital converter (ADC) is presented. The ADC uses six 4-b stages with 2-b interstage redundancy to relax the requirements of Sub-ADC nonlinearity and interstage offset. The ADC, implemented in a 0.18-μm CMOS process, achieves 70.3-dB signal-to-noise and distortion ratio (SNDR), 83.7-dB spurious free dynamic range (SFDR) and 11.3 effective number of bit (ENOB) with 30-MHz input at full 100-MHz sampling rate. The ADC dissipates 342mW from 3.3-V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; 2b interstage redundancy; CMOS process; analog-to-digital converter; frequency 100 MHz; frequency 30 MHz; interstage offset; pipelined A/D converter; power 342 mW; size 0.18 mum; subADC nonlinearity; voltage 3.3 V; CMOS integrated circuits; Capacitors; Clocks; Latches; Pipelines; Redundancy; Solid state circuits;
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
DOI :
10.1109/ISICIR.2014.7029486
