A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizers

Author

Zhixiong Ren ; Kefeng Zhang ; Lanqi Liu ; Cong Li ; Xiaofei Chen ; Dongsheng Liu ; Zhenglin Liu ; Xuecheng Zou

Author_Institution

Sch. of Opt. & Electron. Inf., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2014

fDate

10-12 Dec. 2014

Firstpage

544

Lastpage

547

Abstract

A 1.9GHz linear CMOS power amplifier (PA) using a newly proposed power combiner for higher output power is presented. The PA adopts MOS-level linearizers including the multiple gated transistors (MGTR) and PMOS compensation to reduce the non-linearity induced by the g_m3 and C_gs, which are the dominant harmonic distortion sources. The schematic simulation results demonstrate a gain of 28.9dB, a maximum output power of 33dBm with 34.27% of peak power added efficiency (PAE) and -25dBc IMD3 at 26dBm output power, reaching to excellent tradeoffs between efficiency and linearity.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; power combiners; MGTR; MOS-level linearizers; PA; PAE; PMOS compensation; frequency 1.9 GHz; linear CMOS power amplifier; multiple gated transistors; nonlinearity reduction; power added efficiency; power combiner; CMOS integrated circuits; Capacitance; Logic gates; MOS devices; Power amplifiers; Power combiners; Power generation; IMD3; IMD5; Linearity; PAE; Power amplifier (PA); gm3 cancellation; inter-modulation distortion (IMD);

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2014 14th International Symposium on

Conference_Location

Singapore

Type

conf

DOI

10.1109/ISICIR.2014.7029494

Filename

7029494