Analysis of limit cycles in a two-transistor saturable-core parallel inverter

One of the earliest-developed and still widely-used dc to square-wave inverters is the Royeror Uchrin-Taylor configuration shown in Fig. 1. Although the circuit is composed of very few components, its proper operation depends on complex interactions of the transformer as it switches between its unsaturated and saturated regions, and the tow transistors as they switch between cut-off and saturation. Numerous qualitative descriptions of the operation of this circuit have been presented; however, the complexities introduced by the multiple nonlinearities are such that few mathematically based analyses have been presented, and these have been rather limited in scope (1,2,3,4). The analysis presented in this paper provides insight not only into steady-state operation but also into the transient behavior of the circuit. It also makes evident the influence of certain small, often neglected, parasitic elements such as winding capacitance, transformer saturation inductance, and semiconductor junction capacitances.