Title :
VLSI implementation of a sequential Monte Carlo receiver
Author :
Shabany, Mahdi ; Gulak, P. Glenn
Author_Institution :
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.
Abstract :
A systolic VLSI architecture is developed for a sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The architecture exploits the parallelism intrinsic to the algorithm. The SMC receiver consists of the SMC core, weight calculator, and sampler. Hardware efficient architectures for each functional block are proposed. Detailed features of various mappings of the proposed VLSI architecture for the SMC core are studied. Performance analyzes at both the architecture level and system level, are also presented
Keywords :
Monte Carlo methods; VLSI; channel estimation; radio receivers; signal detection; VLSI implementation; data detection; joint channel estimation; parallel algorithm; sequential Monte Carlo receiver; systolic VLSI architecture; weight calculator; Channel estimation; Decision support systems; Filters; Hardware; Monte Carlo methods; Sliding mode control; State estimation; State-space methods; Very large scale integration; Yttrium;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693360
