DocumentCode :
2545468
Title :
A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture
Author :
Yamasaki, Hideo ; Shibata, Tadashi
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
fYear :
2005
fDate :
12-16 Sept. 2005
Firstpage :
121
Lastpage :
124
Abstract :
A feature-extraction and vector-generation VLSI has been developed for real-time image recognition. An arrayed-shift-register architecture has allowed us to seamlessly scan a wide-area image of interest with a 64 × 64 recognition window and generate a 64-dimension feature vector at each pixel location for on-the-fly recognition. A prototype chip was designed and fabricated in a 0.18-μm 5-metal CMOS technology. A high-speed feature vector generation less than 9.7ns has been experimentally demonstrated. It is possible to scan a VGA-size image at a rate of 5 frames/sec, thus generating as many as 1.5 × 106 feature vectors in a second for recognition. This is 104 times faster than software processing running on a 3GHz CPU.
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; feature extraction; image recognition; logic arrays; real-time systems; shift registers; 0.18 micron; 3 GHz; CMOS technology; feature vector generation; image feature extraction; real-time image recognition; shift register arrays; vector generation VLSI; CMOS technology; Data mining; Face detection; Image edge detection; Image recognition; Object recognition; Pixel; Real time systems; Robustness; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
Type :
conf
DOI :
10.1109/ESSCIR.2005.1541574
Filename :
1541574
Link To Document :
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