A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture

A feature-extraction and vector-generation VLSI has been developed for real-time image recognition. An arrayed-shift-register architecture has allowed us to seamlessly scan a wide-area image of interest with a 64 × 64 recognition window and generate a 64-dimension feature vector at each pixel location for on-the-fly recognition. A prototype chip was designed and fabricated in a 0.18-μm 5-metal CMOS technology. A high-speed feature vector generation less than 9.7ns has been experimentally demonstrated. It is possible to scan a VGA-size image at a rate of 5 frames/sec, thus generating as many as 1.5 × 10⁶ feature vectors in a second for recognition. This is 10⁴ times faster than software processing running on a 3GHz CPU.