Title :
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures
Author :
Fujita, S. ; Noguchi, H. ; Ikegami, K. ; Takeda, S. ; Nomura, K. ; Abe, K.
Author_Institution :
Adv. LSI Technol. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
This paper presents novel ultra-low power processor based on “Normally-off (N-off)” architecture, on which processors can remain in “off state” even during a short standby state. To realize “N-off” for high-performance (HP-) processors, we have developed novel STT-MRAM circuits and nonvolatile cache memories using them.
Keywords :
MRAM devices; cache storage; low-power electronics; HP-processor; N-off architecture; STT-MRAM-based last level cache; high performance ultralow power processor; nonvolatile cache memory; normally-off architecture; spin torque transfer magnetic random access memory; Cache memory; Central Processing Unit; Clocks; Nonvolatile memory; Power supplies; Program processors; Random access memory;
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
DOI :
10.1109/ISICIR.2014.7029504
