DocumentCode :
254562
Title :
An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1,2n + 1}
Author :
Siewobr, H. ; Gbolagade, K.A. ; Cotofana, S.
Author_Institution :
Dept. of Comput. Sci., Univ. for Dev. Studies, Navrongo, Ghana
fYear :
2014
fDate :
10-12 Dec. 2014
Firstpage :
508
Lastpage :
511
Abstract :
In this paper, a new four moduli set {2n/2 ± 1, 22n+1,2n + 1} is proposed together with a two level Chinese Remainder Theorem (CRT) based reverse converter for efficient residue number system arithmetic. The CRT is simplified to obtain a converter that is cheaper and faster than the best known state of the art converters. Experimental results obtained from FPGA implementation suggest that on average, the proposed converter is 27.96% and 21.68% better than the state of the art converter for the moduli set {2n, 2n/2 - 1, 2n/2 + 1, 22n+1 - 1} interms of area and delay, respectively. Additionally, when compared with the state of the art area and speed efficient converters for the {2n, 2n - 1, 2n + 1, 2n+1 - 1} moduli set, the proposed converter improved delay by 68.76% and 55.16% and area by 65.05% and 71.35%, respectively.
Keywords :
field programmable gate arrays; residue number systems; set theory; CRT based reverse converter; Chinese remainder theorem; FPGA; efficient residue number system arithmetic; moduli set {2n/2 ± 1, 22n+1,2n + 1}; residue-to-binary converter; Circuits and systems; Computer architecture; Computers; Delays; Educational institutions; Electronic mail; Libraries; Chinese Remainder Theorem; Mixed Radix Conversion; Moduli Set; Residue Number System; Reverse Converter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
Type :
conf
DOI :
10.1109/ISICIR.2014.7029510
Filename :
7029510
Link To Document :
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