Progress of FD-SOI technology for monolithic pixel detectors

Author

Okihara, Masao ; Kasai, Hiroyuki ; Miura, Naruhisa ; Kuriyama, Naoya ; Nagatomo, Yoshiki ; Hatsui, Takaki ; Omodani, Motohiko ; Miyoshi, Takanori ; Arai, Yutaro

Author_Institution

LAPIS Semicond. Co., Ltd., Yokohama, Japan

fYear

2012

fDate

Oct. 27 2012-Nov. 3 2012

Firstpage

471

Lastpage

474

Abstract

We have been developing the 0.2 μm fully-depleted Silicon On Insulator (SOl) CMOS technology for monolithic pixel detectors. In order to improve the sensor´s sensitivity, 8 inch FZ wafer is introduced for handle substrate in SO! wafer. Stitching technology is also developed to get large detector chip area. Furthermore, nested well structure for the p-n junction and double-SOI structure are investigating for reducing the radiation damage and crosstalk between electrical circuitry in top silicon layer and sensors at substrate. In this document, recent progress of process technology for pixel detector is described.

Keywords

CMOS integrated circuits; X-ray apparatus; p-n junctions; radiation effects; semiconductor counters; silicon-on-insulator; FD-SOI technology; FZ wafer; SO! wafer; X-ray pixel detectors; double-SO! structure; electrical circuitry; fully-depleted silicon on insulator CMOS technology; large detector chip area; monolithic pixel detectors; p-n junction; process technology; radiation damage; sensor sensitivity; size 0.2 mum; size 8 inch; stitching technology; top silicon layer;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE

Conference_Location

Anaheim, CA

ISSN

1082-3654

Print_ISBN

978-1-4673-2028-3

Type

conf

DOI

10.1109/NSSMIC.2012.6551151

Filename

6551151