Title :
Layer assignment for yield enhancement
Author :
Chen, Zhan ; Kore, Israel
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; integrated circuit yield; network routing; Kernighan-Lin algorithm; benchmark circuits; critical area minimization; defect sensitivity; greedy algorithm; layer assignment problem; network bipartitioning problem; primal-dual algorithm; vias; yield enhancement; Artificial intelligence; Circuit faults; Circuit synthesis; Costs; Greedy algorithms; Manufacturing; Minimization methods; Routing; Very large scale integration; Wire;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-7107-6
DOI :
10.1109/DFTVS.1995.476950
