• DocumentCode
    254574
  • Title

    A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout

  • Author

    Su-Yan Fan ; Man-Kay Law ; Pui-In Mak ; Martins, R.P.

  • Author_Institution
    State-Key Lab. of Analog & Mixed-Signal, Univ. of Macau, Macao, China
  • fYear
    2014
  • fDate
    10-12 Dec. 2014
  • Firstpage
    388
  • Lastpage
    391
  • Abstract
    A fully-digital capacitive sensor readout circuit based on capacitance controlled oscillators is presented. A two-step quantization scheme using SAR for coarse conversion and ΔΣ for fine conversion is introduced to extend the sensor input range while preserving the sensing accuracy. Systematic error analysis and optimization for the finite switch on-resistance and buffer input dependent delay are also outlined. Power supply insensitivity is ensured by the use of a pseudo-differential architecture and a ratiometric readout scheme. The complete sensor readout is implemented in a standard 0.18μm CMOS process. Simulation results show that the sensor readout circuit can achieve a wide input range from 1.5 to 6.5pF and a worst case power supply rejection ratio of 0.65% from 0.3V to 0.6V. For the ΔΣ conversion, a resolution of 7.4b at a conversion frequency of 318 Hz with an input capacitance of 4pF and a 0.3V supply is achieved. An average power is 37.5nW at 0.3V with a 4pF input capacitance, corresponding to a Figure-of-Merit (FoM) of 350fJ/conv-step.
  • Keywords
    CMOS integrated circuits; capacitive sensors; circuit optimisation; measurement errors; oscillators; readout electronics; CMOS process; buffer input dependent delay; capacitance 1.5 pF to 6.5 pF; capacitance controlled oscillators; finite switch on-resistance optimization; frequency 318 Hz; fully-digital SAR capacitive sensor readout circuit; power 37.5 nW; power supply insensitivity; power supply rejection ratio; pseudodifferential architecture; ratiometric readout scheme; size 0.18 mum; supply voltage tolerant capacitive sensor readout; systematic error analysis; two-step quantization scheme; voltage 0.3 V; Capacitance; Capacitive sensors; Capacitors; Delays; Simulation; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits (ISIC), 2014 14th International Symposium on
  • Conference_Location
    Singapore
  • Type

    conf

  • DOI
    10.1109/ISICIR.2014.7029516
  • Filename
    7029516