Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

Author

Huang, Zhangcai ; Yu, Hong ; Kurokawa, Atsushi ; Inoue, Yasuaki

Author_Institution

Graduate Sch. of Inf., Waseda Univ., Kitakyushu

fYear

2007

fDate

23-26 Jan. 2007

Firstpage

565

Lastpage

570

Abstract

With the scaling of CMOS technology, the overshooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

Keywords

CMOS integrated circuits; integrated circuit modelling; invertors; nanoelectronics; CMOS inverter; CMOS technology; SPICE simulation results; input-to-output coupling capacitance; inverter delay; nanometer technologies; overshooting effect; overshooting time; process variation; short circuit power estimation; Analytical models; CMOS process; CMOS technology; Capacitance; Circuits; Delay effects; Differential equations; Energy consumption; Inverters; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

1-4244-0629-3

Electronic_ISBN

1-4244-0630-7

Type

conf

DOI

10.1109/ASPDAC.2007.358046

Filename

4196092