Analyzing and improving delay defect tolerance in pipelined combinational circuits

Author

Wessels, David ; Muzio, Jon C.

Author_Institution

Dept. of Comput. Sci., Victoria Univ., BC, Canada

fYear

1995

fDate

13-15 Nov 1995

Firstpage

181

Lastpage

188

Abstract

In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit´s tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode

Keywords

clocks; combinational circuits; delays; logic gates; sensitivity analysis; circuit modification; delay defect tolerance; delay-fault-sensitive components; fixed gate delays; floating delay mode; pipelined combinational circuits; Circuit faults; Clocks; Combinational circuits; Computer science; Councils; Delay; Fault diagnosis; Fault tolerance; Logic gates; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,

Conference_Location

Lafayette, LA

ISSN

1550-5774

Print_ISBN

0-8186-7107-6

Type

conf

DOI

10.1109/DFTVS.1995.476951

Filename

476951

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2545872