Title :
Analyzing and improving delay defect tolerance in pipelined combinational circuits
Author :
Wessels, David ; Muzio, Jon C.
Author_Institution :
Dept. of Comput. Sci., Victoria Univ., BC, Canada
Abstract :
In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit´s tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode
Keywords :
clocks; combinational circuits; delays; logic gates; sensitivity analysis; circuit modification; delay defect tolerance; delay-fault-sensitive components; fixed gate delays; floating delay mode; pipelined combinational circuits; Circuit faults; Clocks; Combinational circuits; Computer science; Councils; Delay; Fault diagnosis; Fault tolerance; Logic gates; Upper bound;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-7107-6
DOI :
10.1109/DFTVS.1995.476951
