Design methodology for hardware-efficient fault-tolerant nanoscale circuits

In this paper, we propose to use ensemble dependent matrices for describing combinatorial nanoscale circuits. We then apply various signal-processing techniques, including eigen analysis, and the use of mutual information, for hardware-efficient fault-tolerant nanoscale design at the system level. We find that the condition of an ensemble matrix product determines the circuit´s fault-tolerant capability. If the product matrix is ill-conditioned, the combinatorial circuit is more error-prone. The knowledge gained from this project can be used eventually to develop computer-aided design tools for optimal nanoscale circuit and system design