Title :
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs
Author :
Hassan, Hassan ; Anis, Mohab ; Elmasry, Mohamed
Author_Institution :
Electr. & Comput. Eng. Dept., Waterloo Univ., Ont.
Abstract :
A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.
Keywords :
CMOS digital integrated circuits; circuit CAD; field programmable gate arrays; leakage currents; nanotechnology; 0.13 micron; CMOS process; MTCMOS CAD methodology; MTCMOS FPGA; circuit timing information; nanometer FPGA; subthreshold leakage power reduction; timing-driven algorithm; CMOS technology; Circuits; Delay; Field programmable gate arrays; Logic; Performance loss; Sleep; Sociotechnical systems; Subthreshold current; Timing;
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
DOI :
10.1109/ASPDAC.2007.358065
