DocumentCode :
2546136
Title :
Architecture and design of the AGIPD detector for the European XFEL
Author :
Becker, Jurgen ; Bianco, L. ; Gottlicher, P. ; Graafsma, Heinz ; Hirsemann, H. ; Jack, S. ; Klyuev, A. ; Marras, A. ; Trunk, U. ; Klanner, Robert ; Schwandt, Joern ; Zhang, Juyong ; Dinapoli, R. ; Greiffenberg, D. ; Henrich, B. ; Mozzanica, A. ; Schmitt,
Author_Institution :
Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany
fYear :
2012
fDate :
Oct. 27 2012-Nov. 3 2012
Firstpage :
585
Lastpage :
590
Abstract :
AGIPD is a hybrid pixel detector developed by DESY, PSI, the University of Bonn and the University of Hamburg. The detector is targeted for use at the European XFEL, a source with unique properties: a bunch train of 2700 pulses with> 1012 photons of 12 keV each, only 100 fs long and with a 220 ns spacing, is repeated at a 10 Hz rate. This puts up very demanding requirements: dynamic range has to cover the detection of single photons and extend up to > 104 photons/pixel in the same image, and as many images, as possible have to be recorded in the pixel to be read out between pulse trains. The high photon flux impinging on the detector also calls for a very radiation hard design of sensor and ASIC. The detector will consist of 16 Sensor modules arranged around a central hole for the direct beam. Each made of a single sensor bumpbonded to 2 × 8 readout chips of 64 × 64 pixels in a grid of 200μ pitch. Each pixel of these ASICs contains a charge sensitive preamplifier featuring adaptive gain switching, changing sensitivity in three ranges, and a buffer to provide correlated double sampling (in the highest sensitivity mode). Most of the pixel area, albeit, is used for an analogue memory to record 352 frames. It is operated in random-access mode: data containing bad frames can be overwritten and the memory can be used in the most efficient way. The readout between two bunch trains is arranged via 4 ports: Data from pixels of one row is read in parallel and serialised by 4 multiplexers at the end of the pixel columns and driven off-chip as differential signals. The operation of the ASIC is controlled via a three-line serial interface, using a command based protocol. It is also used to configure the chip´s operational parameters and internal timings.
Keywords :
analogue storage; application specific integrated circuits; position sensitive particle detectors; readout electronics; semiconductor counters; AGIPD detector architecture; AGIPD detector design; ASIC; European XFEL; adaptive gain switching; bunch train; electron volt energy 12 keV; hybrid pixel detector; photon flux; random access mode; three line serial interface; time 100 fs; time 220 ns; 2D detector; Hybrid Pixel Detector; XFEL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE
Conference_Location :
Anaheim, CA
ISSN :
1082-3654
Print_ISBN :
978-1-4673-2028-3
Type :
conf
DOI :
10.1109/NSSMIC.2012.6551175
Filename :
6551175
Link To Document :
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