A self-compensation fixed-width booth multiplier and its 128-point FFT applications

This paper presents a method for compensating the truncation error of fixed-width booth multipliers which keep the input and the output the same bit-width. The truncated part that produces the carry-out bits is replaced with a carry-estimation equation. In order to reduce the truncation error, different input-width multipliers will have different carry-estimation equations. Simulation results show that our self-compensation method can lead to 85 % reduction of truncation errors while compared with direct-truncated multipliers, as well as 40% reduction in area of a multiplier while compared with traditional booth multipliers. In contrast with the 128-point fast Fourier transform (FFT) using traditional booth multipliers, our approach has 10% area reduction but only 1 dB SQNR loss