Architectural exploration for on-chip, online learning in spiking neural networks

In the recent past there has been an increasing demand for area and energy efficient on-chip implementation of Machine Learning techniques. In this context we have proposed area and power optimized architectures for hardware implementation of a recently proposed supervised learning technique named Network Rewiring (NRW) for Dendritically Enhanced Readout(DER). We show that for the most optimized architecture there is a 8.5 times reduction in critical resources while the MAE has increased only by 1.76% compared to the non-optimized architecture. Moreover, for accommodating real-time training, we have also proposed an online version of the NRW rule. We also show that, though this online algorithm uses an averaging circuit having 4200 times lesser time constant compared to batch learning, yet it provides comparable performance due to the introduction of a voting mechanism.