Title :
Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme
Author :
Yingnan Cui ; Wei Zhang ; Chaturvedi, V. ; Weichen Liu ; Bingsheng He
Author_Institution :
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
3D-NoC emerges as a potential multi-core architecture delivering high performance, high energy efficiency and great scalability. However, severe thermal challenges due to high power density continue to be a major hurdle in the development of 3D-NoC. In this paper, we propose a novel thermal-aware task scheduling scheme named Bottom-to-Top (B2T) approach to address this challenge. Incorporating communication overhead into analysis based on task graph, this heuristic-based method judiciously performs task allocation on processing units to efficiently minimize the peak temperature and improve the execution time of the applications. Our simulation results demonstrate that our scheme can achieve significant peak temperature reduction (up to 7.95°C) and performance improvement (up to 4%) when compared to other methods.
Keywords :
network-on-chip; 3D-NoC; 3D-network-on-chip; B2T approach; bottom-to-top scheme; communication overhead; execution time; heuristic-based method; multicore architecture; performance improvement; processing units; task allocation; task graph; thermal-aware task scheduling scheme; Heating; Heuristic algorithms; Power demand; Program processors; Scheduling; Scheduling algorithms;
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
DOI :
10.1109/ISICIR.2014.7029547