Title :
Memory testing improvements through different stress conditions
Author :
Majhi, Ananta ; Azimane, Mohamed ; Gronthoud, Guido ; Lousberg, Maurice ; Eichenberger, Stefan ; Bowen, Fred
Author_Institution :
Philips Res., Netherlands
Abstract :
This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products. The above test conditions have been validated to screen out the bad chips on real silicon (on a test-chip) built on CMOS 0.18 μm technology.
Keywords :
CMOS memory circuits; embedded systems; fault diagnosis; integrated circuit testing; integrated memory circuits; stress effects; 0.18 micron; CMOS technology; deep sub-micron embedded memories; memory testing; open defect detection; resistive short detection; stress conditions; test conditions; test-chip; Analytical models; Bridge circuits; CMOS technology; Frequency; Semiconductor device modeling; Semiconductor device testing; Silicon; Stress; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541619
