Electrical measurement of alignment for 3D stacked chips

Author

Canegallo, Roberto ; Mirandola, Mauro ; Fazzi, Alberto ; Magagni, Luca ; Guerrieri, Roberto ; Kaschlun, Karin

Author_Institution

STMicroelectronics, Agrate Brianza, Italy

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

347

Lastpage

350

Abstract

This paper presents an electronic system based on integrated CMOS capacitive sensors that enables to determine the alignment between two chips assembled in a three-dimensional (3D) stacking configuration. Two different interface circuits are described for the on-chip measurement of alignment along vertical Z-axis and lateral X/Y-axis. A test chip has been fabricated in 0.13μm, 6 metal standard CMOS process to test the multi-axis alignment system based on 3D sensors. A capacitive charge variation of 1 fF over 15fF corresponding to a resolution accuracy of 0.5μm over a range of 50μm has been measured. Sensors are 120μm × 30μm and power consumption is 200μW.

Keywords

CMOS integrated circuits; assembling; capacitive sensors; chip scale packaging; electric variables measurement; integrated circuit testing; 0.13 micron; 0.5 micron; 120 micron; 200 muW; 30 micron; 3D sensors; 3D stacked chips; 3D stacking configuration; CMOS capacitive sensors; CMOS process; capacitive charge variation; electrical measurement; electronic system; interface circuits; multi-axis alignment system; on-chip measurement; test chip; Assembly systems; CMOS process; Capacitive sensors; Circuit testing; Electric variables measurement; Integrated circuit measurements; Semiconductor device measurement; Sensor systems; Stacking; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Print_ISBN

0-7803-9205-1

Type

conf

DOI

10.1109/ESSCIR.2005.1541631

Filename

1541631