Title :
High performance circuit techniques for dynamic OR gates
Author :
Kheradmand-Boroujeni, Bahman ; Aezinia, Fatemeh ; Afzali-Kusha, Ali
Author_Institution :
Sch. of Electr. & Comput. Eng., Tehran Univ.
Abstract :
In this paper, two methods for high fan-in dynamic OR gates are proposed. The methods are called high-speed low-swing OR gate (HSLS-OR) and low-power selective evaluate OR gate (LPSE-OR). HSLS-OR contains separate parallel NMOS logic trees in which one controls the evaluation phase of the other ones. This leads to a low voltage swing in the dynamic capacitive nodes. In LPSE-OR, the NMOS logic tree is divided into several successive parts to prevent using strong keepers. Unnecessary parts are disabled in the evaluation phase for saving the power. (16, 32, and 64)-bit HSLS-OR and (32 and 64)-bit LPSE-OR gates are simulated using HSPICE in 65 nm bulk CMOS technology. Compared to the previous works, the new circuits show 34-48% better power delay product (PDP)
Keywords :
CMOS logic circuits; SPICE; high-speed integrated circuits; logic gates; 16 bit; 32 bit; 64 bit; 65 nm; HSLS-OR; HSPICE; LPSE-OR; bulk CMOS technology; dynamic OR gates; dynamic capacitive nodes; high performance circuit techniques; high-speed low-swing OR gate; low-power selective evaluate OR gate; parallel NMOS logic trees; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Clocks; Delay; Energy consumption; MOS devices; Phase noise; Timing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693421
