DocumentCode :
2546847
Title :
Design Consideration of 6.25 Gbps Signaling for High-Performance Server
Author :
Jiang, Jian Hong ; Gai, Weixin ; Hattori, Akira ; Hidaka, Yasuo ; Horie, Takeshi ; Koyanagi, Yoichi ; Osone, Hideki
Author_Institution :
Platform Innovation Group, Fujitsu Labs. of America Inc., Sunnyvale, CA
fYear :
2007
fDate :
23-26 Jan. 2007
Firstpage :
854
Lastpage :
857
Abstract :
As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.
Keywords :
CMOS integrated circuits; high-speed integrated circuits; network servers; 6.25 Gbits/s; 90 nm; CMOS technology; high-performance server; high-speed circuits; high-speed signaling circuits; network data rate; server communication; server interconnect; Backplanes; Bit error rate; CMOS technology; Circuit noise; Dielectric losses; Integrated circuit interconnections; LAN interconnection; Network servers; Signal design; Storage area networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
Type :
conf
DOI :
10.1109/ASPDAC.2007.358096
Filename :
4196142
Link To Document :
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