Title :
System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production
Author :
Yip, Wai-Yeung ; Best, Scott ; Beyene, Wendemagegnehu ; Schmitt, Ralf
Author_Institution :
Platform Solutions, Rambus Inc., Los Altos, CA
Abstract :
This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell Broadband Enginetrade (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A system co-design and co-analysis approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach.
Keywords :
integrated circuit design; integrated memory circuits; memory architecture; microprocessor chips; 3.2 Gbits/s; Cell Broadband Engine processor; IBM; Sony Computer Entertainment; Sony Corporation; Toshiba; XDR memory interface circuit; XDR memory system; interface statistical signal integrity analysis; power delivery system analysis; power delivery system design; system co-analysis; system co-design; Bandwidth; Circuits; Clocks; Costs; Electronic mail; Engines; Random access memory; Signal analysis; Signal processing; Timing;
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
DOI :
10.1109/ASPDAC.2007.358097
