System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production

This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell Broadband Enginetrade (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A system co-design and co-analysis approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach.