Title :
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications
Author :
Somasekhar, Dinesh ; Lu, Shih-Lien ; Bloechel, Bradley ; Dermer, Greg ; Lai, Konrad ; Borkar, Shekhar ; De, Vivek
Author_Institution :
Microprocessor Res. Labs., Intel Labs., Hillsboro, OR, USA
Abstract :
A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110°C. Worst-case refresh period is 100μS at 110°C with refresh power density of 0.18W/cm2. Effective bit density of 42Mb/cm2 is ∼3× better than the best 6T SRAM cache in the same technology.
Keywords :
DRAM chips; MOS capacitors; MOS memory circuits; SRAM chips; logic design; microprocessor chips; 1.5 V; 10 Mbit; 100 mus; 110 C; 15 GByte/s; 150 nm; 197 mW; 9 ns; DRAM chip; MOS storage capacitor; SRAM cache; effective bit density; high-density on-chip memory; microprocessor logic process; refresh power density; unmodified logic process; Argon; Bandwidth; Circuit testing; Counting circuits; Logic arrays; MOS capacitors; Microprocessors; Random access memory; Routing; System performance;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541633
