Title :
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS
Author :
Calhoun, Benton H. ; Chandrakasan, Anantha
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology. We analyze the statistical distribution of SNM with process variation and provide a model for the tail of the PDF that dominates SNM failures.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit noise; statistical distributions; 65 nm; CMOS technology; SRAM bitcells; hold modes; local transistor mismatch; process variation; random doping variation; read modes; static noise margin; statistical distribution; Degradation; Doping; Failure analysis; Inverters; Noise figure; Random access memory; Semiconductor process modeling; Statistical distributions; Temperature dependence; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541635
