Design Methodology for 2.4GHz Dual-Core Microprocessor

Author

Ito, Noriyuki ; Komatsu, Hiroaki ; Kanuma, Akira ; Yoshitake, Akihiro ; Tanamura, Yoshiyasu ; Sugiyama, Hiroyuki ; Yamashita, Ryoichi ; Nabeya, Ken-ichi ; Yoshino, Hironobu ; Yamanaka, Hitoshi ; Yanagida, Masahiro ; Ozeki, Yoshitomo ; Ishizaka, Kinya ; Ko

Author_Institution

Fujitsu Ltd., Kawasaki

fYear

2007

fDate

23-26 Jan. 2007

Firstpage

896

Lastpage

901

Abstract

This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64trade microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.

Keywords

CMOS integrated circuits; built-in self test; logic design; microprocessor chips; 2.4 GHz; 90 nm; CMOS technology; dual-core design; dual-core microprocessor; logic BIST circuit; noise-immune clock distribution circuit; signal integrity analysis; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Delay; Design methodology; Large-scale systems; Microprocessors; Signal analysis; Signal design; BIST; Microprocessor; clock; custom macro; dual-core; signal integrity; test;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

1-4244-0629-3

Electronic_ISBN

1-4244-0630-7

Type

conf

DOI

10.1109/ASPDAC.2007.358103

Filename

4196149