FPGA-based architecture for fast feature extraction with high resolution

Signal processing in real time allows to keep the resolution and sampling frequency of an ADC as well as the data storage size at a reasonable level, providing cost-effective solution for multichannel digitization systems. Modern FPGA are capable of optimal signal processing and can deliver in real time the precision, comparable to offline data processing. An FPGA-based architecture for extracting time and amplitude information of the signal with known shape is described. The matched filter is used to maximize the signal to noise ratio (SNR) in the presence of additive stochastic noise. The timing is determined using quadratic interpolation of the filtered signal. The resulting timing resolution is G*sqrt(N)*TISNR, where G is a shape-dependent constant, T-sampling period. The systematic errors are corrected based on the interpolated time. The performance of the algorithm is demonstrated using Monte-Carlo simulations. The architecture for 16 ADC channels (14-bit, 80 MHz) have been implemented on a low-cost FPGA (ACTEL A3P600) utilizing 80% of the FPGA resources. The described architecture is expected to be used to process signals from the silicon photomultipliers of upgraded PHENIX experiment at RHIC..